JIPS (한국정보처리학회)
Current Result Document :
| 한글제목(Korean Title) |
Selecting a Synthesizable RISC-V Processor Core for Low-cost Hardware Devices |
| 영문제목(English Title) |
Selecting a Synthesizable RISC-V Processor Core for Low-cost Hardware Devices |
| 저자(Author) |
Dennis Agyemanh
Nana Gookyi
Kwangki Ryoo
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| 원문수록처(Citation) |
VOL 15 NO. 06 PP. 1406 ~ 1421 (2019. 12) |
한글내용
(Korean Abstract) |
|
영문내용
(English Abstract) |
The Internet-of-Things (loT) has been deployed in almost every facet of our day to day activities. This is made possible because sensing and data collection devices have been given computing and communication capabilities. The devices implement System-on-Chips (SoCs) that incorporate a lot of functionalities, yet they are severely constrained in terms of memory capacitance, hardware area, and power consumption. With the increase in the functionalities of sensing devices, there is a need for low-cost synthesizable processors to handle control, interfacing, and error processing. The first step in selecting a synthesizable processor core for low-cost devices is to examine the hardware resource utilization to make sure that it fulfills the requirements of the device. This paper gives an analysis of the hardware resource usage of ten synthesizable processors that implement the Reduced Instruction Set Computer Five (RISC-V) Instruction Set Architecture (ISA). All the ten processors are synthesized using Vivado v2018.02. The maximum frequency, area, and power reports are extracted and a comparison is made to determine which processor is ideal for low-cost hardware devices.
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| 키워드(Keyword) |
Hardware Resources
loT
Low-Cost Hardware Devices
RISC-V
SoC
Synthesizable Processors
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| 파일첨부 |
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